1. Field of the Invention
The present invention relates to a high-voltage semiconductor device, and more particularly, to a high-voltage semiconductor device including a conductive structure embedded in an insulation unit between a gate structure and a drain.
2. Description of the Prior Art
With improvement in semiconductor manufacturing, it is conceivable to fabricate control circuits, memories, low-voltage circuits, high-voltage circuits, and the related devices in a single chip for reducing costs and improving performance. And a MOS transistor device, which is widely applied for enlarging currents or signals in a circuit, serving as an oscillator of a circuit, or serving as a switch device of a circuit, is further applied to be the high power device or the high-voltage device based on the development of semiconductor processes. For example, a MOS transistor device, serving as a high-voltage device, is applied in between the internal circuits and the I/O terminals for preventing a large number of charges from suddenly spiking into the internal circuits and thus to avoid the resulted damage to the internal circuit. Additionally, the high-voltage device may also be applied to serve as a program/erase driver in an embedded nonvolatile memory (eNVM) or be applied in a LCD driver to modulate greyscale signals.
In the conventional high-voltage MOS transistor device, the breakdown voltage is enhanced by lowering the lateral electrical field. The types of the conventional high-voltage MOS transistor devices substantially include the high-voltage MOS transistor device with a drift region, such as a double diffused drain MOS (DDDMOS) transistor device and a laterally diffused drain MOS (LDMOS) transistor device and the high-voltage MOS transistor device with shallow trench isolation (STI) disposed at the drain side, such as a field diffused drain MOS (FDMOS) transistor device and a drain extended MOS (DEMOS) transistor device. However, many parts of the structures described above, such as the gate structure, the source region, the drain region, the N-type well, and/or the P-type well, require a specific size for providing sufficient robustness for high voltage. Therefore the high-voltage MOS transistor device often occupies the valuable spaces on the chip and adversely influences integrity level. Additionally, the drain-source-on-state resistance (Ron) will increase while the device area of the high-voltage MOS transistor device increases, and it is difficult to lower the drain-source-on-state resistance of the high-voltage MOS transistor device such as the LDMOS transistor device mentioned above.